The processor would then access the two SIMMs in parallel.

For input or output, each peripheral processor accesses a peripheral device over a communication link called a data channel.

One of the bits in the processor state word (see below) indicates that the processor is accessing data from the stack.

If all 16 processors were accessing different banks of memory, the memory accesses would all be concurrent.

When processors access some data, a copy is made in their local cache, but space remains allocated in the home node.

Either the processor or the video/sound engine could access the memory, but not both, resulting in up to a 10% loss in performance.

Now a system can starve several processors at the same time, notably because only one processor can access the computer's memory at a time.

While the main 256x192 area of the screen was being drawn, the processor could only access memory in 1 out of every 8 t-states.

The benefit of this is that a pipelined processor may access memory from different phases in its pipeline.

That is a parallel computer with a central pool of memory, and any processor can access any bit of memory in constant time.