With pipelined processors, this is not the case.

The performance of a pipelined processor is much harder to predict and may vary widely for different programs.

In such extreme cases, the performance of a pipelined processor could be worse than non-pipelined processor.

On a pipelined processor, all of the stages can be working at once on different instructions.

The canonical implementation of the state machine is an excellent candidate for reduction, and can also be re-implemented as a pipelined processor.

When it was designed, it was a high-performance pipelined processor with core memory.

Very few pipelined processor are designed to exceed 10 stages in real computers.

This assumption is not true on a pipelined processor.

Programs written for a pipelined processor deliberately avoid branching to minimize possible loss of speed.

The benefit of this is that a pipelined processor may access memory from different phases in its pipeline.