This is referred to as a true dependency or flow dependency, and requires the instructions to execute in program order.

All instructions execute in two clock cycles, making performance of the core instruction set deterministic.

It allowing two independent registers to be accessed and instruction with them executed in one machine cycle.

If the trap flag is set, the 8086 will automatically do a type-1 interrupt after each instruction executes.

All these instructions only execute in a single cycle if all the pieces that they need are available on the cache.

Out-of-order execution where instructions execute in any order but without violating data dependencies.

Some instructions compile and execute more efficiently when using these registers for their designed purpose.

Out-of-order execution where instructions execute in any order that does not violate data dependencies.

Starting off, right off the bat, no opcode because you don't need to tell it which instruction to execute.

The tag is marked as unready, because the instruction has not yet executed.