The floating-point instruction cache is also increased in capacity to 24 entries from 20.

The R10000 fetches four instructions every cycle from its instruction cache.

The instruction cache is two-way set-associative and has a 128-byte line size.

It fetches up to four instructions per cycle from the instruction cache.

The chip doubles instruction cache to 256Kb, the same size as the data cache.

In stage one, four instructions are fetched from the instruction cache.

The instruction cache is accessed via a 256-bit bus.

Most machines will have enough instruction cache so that this isn't an issue.

The data cache is direct-mapped for the same reasons as the instruction cache.

Can also cause an increase in instruction cache misses, which may adversely affect performance.