The output C becomes valid during this time - and therefore a 1 gate output can't drive another 1 gate's inputs.

The gate output is dynamic.

This means that its state is held on capacitance at the gate output.

But the output track can cross clock lines and other gate outputs, all of which can change the charge on the capacitor.

Lumped C. The entire wire capacitance is applied to the gate output, and the delay through the wire itself is ignored.

A perfect logic gate would have infinite input impedance and zero output impedance, allowing a gate output to drive any number of gate inputs.

The dynamic power component, related to the charging and discharging of the load capacitance at the gate output.

A signal, or gate output, is stuck at a 0 or 1 value, independent of the inputs to the circuit.

The AND gate output therefore becomes LOW and the integrator ramps down to zero.

In set theoretic terms, this is equivalent to the intersection of the input event sets, and the probability of the and gate output is given by: