Separate instruction and data caches (512 B to 64 kB)

Improvements were 64 KB instruction and data caches.

Although it was based on the 21064A, the 21066A did not have the 16 KB instruction and data caches.

The most common modification includes separate instruction and data caches backed by a common address space.

The MC88100 had separate instruction and data caches.

The 68030 features on-chip instruction and data caches of 256 bytes each.

Register files are good tools for computing because they have high bandwidth and very low latency, compared to memory references via data caches.

Pipelines with separate instruction and data caches, now predominant, are said to have a Harvard architecture.

The first consisted of separate 2 KB instruction and data caches.

Four dies implement the level 1 (L1) instruction and data caches, which require two dies each.