Hard cores, by the nature of their low-level representation, offer better predictability of chip performance in terms of timing performance and area.

For example, an architectural decision to pipeline a logic function can have a far greater impact on total chip performance than any amount of postrouting fix-up.

The Power 5 technology, I.B.M. researchers say, was designed more for customers than is the case in traditional microprocessor development, which tends to focus on raw chip performance.

The technology, known as S.O.I. for silicon on insulator, bolsters chip performance up to 35 percent by allowing chips to handle power much more efficiently.

That technology, known as S.O.I., for silicon-on-insulator, also speeds up chip performance and reduces power needs.

"There's been talk that we've started to hit the physical limitations of chip performance," he said.

According to Moore's law, each new technology generation doubles the number of transistors on chip increasing performance by 40%.

The move is intended to reflect Advanced Micro's contention that megahertz, or millions of cycles per second, are an outdated way of measuring overall chip performance.

Not so long ago, experts predicted that chip performance would reach the limits of Moore's Law long before reaching a gigahertz.

In the time it has taken chip performance to improve 10 times, battery life has improved two times.