Since the SSE2 processor extension, Intel has provided such a functionality in CPU hardware, which rounds denormalized numbers to zero.

The company's patented multi-core CPU hardware enables this intelligent switching at up to 10 Gbit/s throughput.

In fact, proper locking ultimately depends upon the CPU hardware itself providing a method of atomic instruction stream synchronization.

CPU hardware dynamically checks for data dependencies between instructions at run time.

Bubble sort also interacts poorly with modern CPU hardware.

The 10 PPs were implemented virtually; there was CPU hardware only for a single PP.

This CPU hardware was shared and operated on 10 PP register sets which represented each of the 10 PP states (similar to modern multithreading processors).

CPU hardware dynamically checks for data dependencies between instructions at run time (versus software checking at compile time)

Mode protection may extend to resources beyond the CPU hardware itself.

(A full turn of the wheel, when graphics hardware becomes more fully generalized and less distinguishable from general-purpose CPU hardware, is still a bit further off.)